273 lines
6.2 KiB
C
273 lines
6.2 KiB
C
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#ifndef ASM_CPU_H
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#define ASM_CPU_H
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#ifndef __ASSEMBLY__
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#include "WL82.h"
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#if ((!defined __cplusplus) && (!defined BOOL_DEFINE_CONFLICT))
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typedef unsigned char bool;
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#endif
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typedef unsigned char u8, BOOL, uint8_t;
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typedef char s8;
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typedef signed char int8_t;
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typedef unsigned short u16, uint16_t, u_int16_t;
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typedef signed short s16, int16_t;
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typedef unsigned int u32, uint32_t;
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typedef signed int s32;
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typedef unsigned long long u64;
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typedef u32 FOURCC;
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typedef long long s64;
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typedef unsigned long long u64, uint64_t;
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#endif
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#define ___trig __asm__ volatile ("trigger")
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#ifndef BIG_ENDIAN
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#define BIG_ENDIAN 0x3021
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#endif
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#ifndef LITTLE_ENDIAN
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#define LITTLE_ENDIAN 0x4576
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#endif
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#define CPU_ENDIAN LITTLE_ENDIAN
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#define CPU_CORE_NUM 2
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#define __NONCPU_ADDR__ ((u8 *)0x04000000)
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#define __SFC_ADDR_BEGIN__ ((u32)0x2000000)
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#define __SFC_ADDR_END__ ((u32)0x4000000)
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#define NO_CACHE_ADDR(addr) \
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(u32)(((u32)(addr) >=0x4000000)?((u32)(addr)+0x4000000):(u32)(addr))
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#define CPU_ADDR(addr) \
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(u32)(((u32)(addr) >=0x8000000)?((u32)(addr)-0x4000000):(u32)(addr))
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#define CPU_TASK_CLR(a)
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#define CPU_TASK_SW(a) \
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do { \
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extern void wdt_clear(void);\
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q32DSP(0)->ILAT_SET|=BIT(7-a); \
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wdt_clear(); \
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} while (0)
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#define SFC_WAIT() __asm_csync();\
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while (JL_SFC->CON & BIT(31));
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#define CACHE_WAIT() __asm_csync();\
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while (!(corex2(0)->CACHE_CON & BIT(14)));
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#define CPU_INT_NESTING 2
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#ifndef __ASSEMBLY__
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__attribute__((always_inline))
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static inline u32 rand32()
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{
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return JL_RAND->R64L;
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}
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__attribute__((always_inline))
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static inline int current_cpu_id()
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{
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unsigned id;
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asm volatile("%0 = cnum" : "=r"(id) ::);
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return id ;
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}
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extern int cpu_in_irq(void);
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extern int cpu_irq_disabled();
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__attribute__((always_inline))
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static inline int data_sat_s16(int ind)
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{
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__asm__ volatile(
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" %0 = sat16(%0)(s) \t\n"
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: "=&r"(ind)
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: "0"(ind)
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:);
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return ind;
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}
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__attribute__((always_inline))
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static inline u32 reverse_u32(u32 data32)
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{
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#if 1
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u8 *dataptr = (u8 *)(&data32);
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data32 = (((u32)dataptr[0] << 24) | ((u32)dataptr[1] << 16) | ((u32)dataptr[2] << 8) | (u32)dataptr[3]);
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#else
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__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(data32) : "0"(data32) :);
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#endif
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return data32;
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}
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__attribute__((always_inline))
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static inline u32 reverse_u16(u16 data16)
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{
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u32 retv;
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#if 1
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u8 *dataptr = (u8 *)(&data16);
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retv = (((u32)dataptr[0] << 8) | ((u32)dataptr[1]));
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#else
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retv = ((u32)data16) << 16;
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__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(retv) : "0"(retv) :);
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#endif
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return retv;
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}
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#endif
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#ifndef __ASSEMBLY__ //assembly
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#define __asm_csync() \
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do { \
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asm volatile("csync;"); \
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} while (0)
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#include "asm/irq.h"
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#include "generic/printf.h"
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#include "system/generic/log.h"
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#define arch_atomic_read(v) \
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({ \
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__asm_csync(); \
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(*(volatile int *)&(v)->counter); \
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})
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extern volatile int cpu_lock_cnt[];
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extern volatile int irq_lock_cnt[];
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extern volatile char cpu1_run_flag;
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extern void __local_irq_disable(void);
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extern void __local_irq_enable(void);
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extern int __local_irq_lock_cnt(void);
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extern void local_irq_disable(void);
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extern void local_irq_enable(void);
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extern void sys_local_irq_disable(void);
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extern void sys_local_irq_enable(void);
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#if 0
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#define arch_spin_lock(lock) \
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do { \
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int ret = false; \
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if(cpu_lock_cnt[current_cpu_id()]++ == 0) \
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asm volatile("lockset;"); \
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__asm_csync(); \
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if (!(lock)->rwlock) { \
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ret = true; \
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(lock)->rwlock = 1; \
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} \
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__asm_csync(); \
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if (--cpu_lock_cnt[current_cpu_id()] == 0) \
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asm volatile("lockclr;"); \
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if (ret) \
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break; \
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}while(1)
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#define arch_spin_unlock(lock) \
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do { \
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__asm_csync(); \
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(lock)->rwlock = 0; \
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}while(0)
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#else
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#define arch_spin_lock(lock) do{__asm_csync();__asm__ volatile ( "1: \n\t" "testset b[%0] \n\t" "ifeq goto 1b \n\t" :: "r"(&(lock)->rwlock));__asm_csync();}while(0)
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#define arch_spin_unlock(lock) do{__asm_csync();(lock)->rwlock = 0;}while(0)
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#endif
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#define CPU_SR_ALLOC() \
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// int flags
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#define CPU_CRITICAL_ENTER() \
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do { \
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sys_local_irq_disable(); \
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}while(0)
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#define CPU_CRITICAL_EXIT() \
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do { \
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sys_local_irq_enable(); \
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}while(0)
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__attribute__((always_inline))
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static inline void cpu_reset(void)
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{
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extern void log_flush();
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extern void P33_SYSTEM_RESET(void);
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// log_flush();
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P33_SYSTEM_RESET();
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while (1);
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}
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__attribute__((always_inline))
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static inline void system_reset(void)
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{
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extern void log_flush();
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extern void CORE_SYSTEM_RESET(void);
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// log_flush();
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CORE_SYSTEM_RESET();
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while (1);
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}
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extern void cpu_assert_debug();
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extern const char *os_current_task_rom();
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extern const int config_asser;
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#define ASSERT(a,...) \
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do { \
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if(config_asser){\
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if(!(a)){ \
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printf("file:%s, line:%d, task:%s", __FILE__, __LINE__,os_current_task_rom()); \
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printf("ASSERT-FAILD: " #a " " __VA_ARGS__); \
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cpu_assert_debug(); \
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} \
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}else {\
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if(!(a)){ \
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cpu_reset(); \
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}\
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}\
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}while(0);
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#endif
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/*#define MULU(Rm,Rn) __builtin_pi32_umul64(Rm,Rn);*/
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/*#define MUL(Rm,Rn) __builtin_pi32_smul64(Rm,Rn);*/
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/*#define MLA(Rm,Rn) __builtin_pi32_smla64(Rm,Rn);*/
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/*#define MLA0(Rm,Rn) MUL(Rm,Rn);*/
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/*#define MLS(Rm,Rn) __builtin_pi32_smls64(Rm,Rn);*/
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/*#define MLS0(Rm,Rn) MUL(-Rm,Rn);*/
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/*#define MRSIS(Rm,Rn) (Rm = __builtin_pi32_sreadmacc(Rn));//mac read right shift imm&sat*/
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/*#define MRSRS(Rm,Rn) (Rm = __builtin_pi32_sreadmacc(Rn)); //mac read right shift reg&sat*/
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/*#define MACCLR() __asm__ volatile ("clrmacc");*/
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/*#define MACSET(h,l) __asm__ volatile ("mov maccl, %0; mov macch, %1"::"r" (l), "r" (h));*/
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/*#define MACRL(l) __asm__ volatile ("mov %0, maccl":"=r" (l));*/
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/*#define MACRH(l) __asm__ volatile ("mov %0, macch":"=r" (l));*/
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/*#define MULSIS(Ro,Rm,Rn,Rp) MUL(Rm, Rn); MRSIS(Ro, Rp);*/
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/*#define MULSRS(Ro,Rm,Rn,Rp) MUL(Rm, Rn); MRSRS(Ro, Rp);*/
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#define CPU_RAND() (JL_RAND->R64L)
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#endif
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