223 lines
11 KiB
C
223 lines
11 KiB
C
#ifndef _ETHMAC_H_
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#define _ETHMAC_H_
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#include "generic/typedef.h"
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#include "eth/eth_phy.h"
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//#include "usart.h"
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/*
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CHIP_PIN 3SL150 3SL340 MII_MODE RMII_MODE
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PE2---------P82---------PE2-------------MII_RX2----------NC
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PE3---------P83---------PE3-------------MII_RX3----------NC
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PH0---------PE0---------PM0-------------NC/MII_TXERR-----NC/RMII_TXERR
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PH1---------PE1---------PM1-------------MII_RXCLK--------NC
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PH2---------PE2---------PM2-------------NC/MII_COL-------NC/RMII_COL
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PH3---------PE3---------PM3-------------MII_RXDV---------NC/RMII_RXDV
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PH4---------PE4---------PM4-------------MII_TX2----------NC
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PH5---------PE5---------PM5-------------MII_TX3----------NC
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PH6---------PE6---------PM6-------------MDC--------------MDC
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PH7---------PE7---------PM7-------------MDIO-------------MDIO
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PH8---------PF0---------PN0-------------MII_TX0----------RMII_TX0
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PH9---------PF1---------PN1-------------MII_TX1----------RMII_TX1
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PH10--------PF2---------PN2-------------MII_TXEN---------RMII_TXEN
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PH11--------PF3---------PN3-------------NC/MII_RXERR-----NC/RMII_RXER
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PH12--------PF4---------PN4-------------MII_TXCLK--------RMII_REFCLK
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PH13--------PF5---------PN5-------------MII_CRS----------RMII_CRSDV
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PH14--------PF6---------PN6-------------MII_RX0----------RMII_RX0
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PH15--------PF7---------PN7-------------MII_RX1----------RMII_RX1
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*/
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/* Ethernet configuration registers */
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typedef struct _oeth_regs {
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volatile u32 moder; /* Mode Register */
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volatile u32 int_src; /* Interrupt Source Register */
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volatile u32 int_mask; /* Interrupt Mask Register */
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volatile u32 ipgt; /* Back to Bak Inter Packet Gap Register */
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volatile u32 ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */
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volatile u32 ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */
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volatile u32 packet_len; /* Packet Length Register (min. and max.) */
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volatile u32 collconf; /* Collision and Retry Configuration Register */
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volatile u32 tx_bd_num; /* Transmit Buffer Descriptor Number Register */
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volatile u32 ctrlmoder; /* Control Module Mode Register */
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volatile u32 miimoder; /* MII Mode Register */
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volatile u32 miicommand; /* MII Command Register */
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volatile u32 miiaddress; /* MII Address Register */
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volatile u32 miitx_data; /* MII Transmit Data Register */
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volatile u32 miirx_data; /* MII Receive Data Register */
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volatile u32 miistatus; /* MII Status Register */
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volatile u32 mac_addr0; /* MAC Individual Address Register 0 */
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volatile u32 mac_addr1; /* MAC Individual Address Register 1 */
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volatile u32 hash_addr0; /* Hash Register 0 */
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volatile u32 hash_addr1; /* Hash Register 1 */
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volatile u32 txctrl; /* Transmit control frame Register */
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volatile u32 rxctrl; /* Rx control frame Register */
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volatile u32 wbdbg; /* Wishbone state machine debug information */
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} oeth_regs;
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/* Ethernet buffer descriptor */
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typedef struct _oeth_bd {
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volatile u32 len_status;
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volatile u32 addr; /* Buffer address */
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} oeth_bd;
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struct oeth_data {
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u8 *data;
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u32 data_len;
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};
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/* Tx BD */
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#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */
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#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */
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#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */
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#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */
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#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */
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#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */
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#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */
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#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */
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#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */
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#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */
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#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */
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#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \
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OETH_TX_BD_RETRY | \
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OETH_TX_BD_RETLIM | \
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OETH_TX_BD_LATECOL | \
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OETH_TX_BD_DEFER | \
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OETH_TX_BD_CARRIER)
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#define OETH_TX_BD_ERR_STATS (OETH_TX_BD_UNDERRUN | \
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OETH_TX_BD_RETRY | \
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OETH_TX_BD_RETLIM | \
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OETH_TX_BD_LATECOL | \
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OETH_TX_BD_DEFER | \
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OETH_TX_BD_CARRIER)
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/* Rx BD */
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#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */
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#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */
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#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */
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#define OETH_RX_BD_CF 0x0100 /* Rx BD Control Frame */
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#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */
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#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */
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#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */
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#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */
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#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */
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#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */
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#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */
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#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */
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#define OETH_RX_BD_STATS (OETH_RX_BD_CF | \
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OETH_RX_BD_MISS | \
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OETH_RX_BD_OVERRUN | \
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OETH_RX_BD_INVSIMB | \
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OETH_RX_BD_DRIBBLE | \
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OETH_RX_BD_TOOLONG | \
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OETH_RX_BD_SHORT | \
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OETH_RX_BD_CRCERR | \
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OETH_RX_BD_LATECOL)
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#define OETH_RX_BD_ERR_STATS (OETH_RX_BD_OVERRUN | \
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OETH_RX_BD_INVSIMB | \
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OETH_RX_BD_DRIBBLE | \
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OETH_RX_BD_TOOLONG | \
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OETH_RX_BD_SHORT | \
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OETH_RX_BD_CRCERR | \
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OETH_RX_BD_LATECOL)
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/* MODER Register */
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#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */
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#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */
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#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */
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#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */
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#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */
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#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */
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#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */
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#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */
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#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */
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#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */
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#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */
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//#define OETH_MODER_RST 0x00000800 /* Reset MAC */
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#define OETH_MODER_MODE 0x00000800 /* MII/RMII mode */
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#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */
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#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */
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#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */
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#define OETH_MODER_PAD 0x00008000 /* Pad Enable */
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#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */
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/* Interrupt Source Register */
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#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */
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#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */
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#define OETH_INT_RXB 0x00000004 /* Receive Frame IRQ */
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#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */
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#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */
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#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */
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#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */
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/* Interrupt Mask Register */
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#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */
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#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */
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#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */
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#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */
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#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */
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#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */
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#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */
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/* Control Module Mode Register */
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#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */
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#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */
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#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */
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/* MII Mode Register */
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#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */
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#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */
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#define OETH_MIIMODER_RST 0x00000200 /* MII Reset */
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/* MII Command Register */
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#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */
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#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */
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#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
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/* MII Address Register */
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#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */
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#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */
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/* MII Status Register */
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#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
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#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */
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#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */
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#define RMII_MODE 1
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#define MII_MODE 0
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#define oeth_puts puts
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#define oeth_printf printf
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void oeth_clean_current_bd(struct eth_platform_data *__data);
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int ethmac_setup(struct eth_platform_data *__data);
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void oeth_enable_oeth_txrx(void);
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void oeth_disable_oeth_txrx(void);
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/*针对lwip底层收发包机制定制的函数,加强耦合使得效率更高*/
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u8 *oeth_get_txaddr(void);//发送一个数据包,最大buflen不能超过1514Byte,要求数据指针地址4字节对齐
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void oeth_tx_packet(u16 length);
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void oeth_tx_pkt_addr_word_align(void *pkt, u16 length);//发送一个数据包,最大buflen不能超过1514Byte,要求数据指针地址4字节对齐
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//通用收发包函数
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u8 oeth_tx_pkt(void *buf, u16 buf_len);
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int oeth_rx_pkt(void *arg, u8 *buf, u16 buf_len);
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void oeth_rx_pkt_test(void *arg);
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u16 ethernet_checksum(void *dataptr, u32 len);
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int oeth_get_rxpkt_addr_len(struct eth_platform_data *__data, struct oeth_data *_oeth_data);
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u32 check_all_rx_bd();
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void clear_all_rx_bd();
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u32 check_all_tx_bd();
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void tx_speed();
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void rx_speed();
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void check_oeth_stats();
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void reset_mac(void);
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#endif
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