459 lines
9.9 KiB
C
459 lines
9.9 KiB
C
#ifndef __CLOCK_HW_H__
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#define __CLOCK_HW_H__
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#include "typedef.h"
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// #define CLOCK_HAL_DEBUG
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#ifdef CLOCK_HAL_DEBUG
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#define RC_EN(x)
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#define TEST_SEL(x)
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#define OSC_CLOCK_IN(x)
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//for MACRO - OSC_CLOCK_IN
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enum {
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OSC_CLOCK_IN_BT_OSC = 0,
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OSC_CLOCK_IN_RTOSC_H,
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OSC_CLOCK_IN_RTOSC_L,
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OSC_CLOCK_IN_PAT,
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};
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#define MAIN_CLOCK_SEL(x)
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//for MACRO - CLOCK_IN
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enum {
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MAIN_CLOCK_IN_RC = 0,
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MAIN_CLOCK_IN_BTOSC = 4,
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MAIN_CLOCK_IN_RTOSC_H,
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MAIN_CLOCK_IN_RTOSC_L,
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MAIN_CLOCK_IN_PLL,
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MAIN_CLOCK_IN_PAT, //for tes
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};
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#define SFR_MODE(x)
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enum {
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SFR_CLOCK_IDLE = 0,
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SFR_CLOCK_ALWAYS_ON,
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};
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#define PB0_CLOCK_OUT(x)
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#define PA2_CLOCK_OUT(x)
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#define USB_CLOCK_IN(x)
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//for MACRO - USB_CLOCK_IN
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enum {
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USB_CLOCK_IN_PLL48M = 0,
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USB_CLOCK_IN_DISABLE,
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USB_CLOCK_IN_LSB,
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USB_CLOCK_IN_DISABLE_PAD,
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};
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#define DAC_CLOCK_IN(x)
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//for MACRO - DAC_CLOCK_IN
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enum {
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DAC_CLOCK_IN_PLL24M = 0,
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DAC_CLOCK_IN_OSC,
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DAC_CLOCK_IN_LSB,
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DAC_CLOCK_IN_DISABLE_PAD,
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};
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#define APC_CLOCK_IN(x)
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//for MACRO - APC_CLOCK_IN
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enum {
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APC_CLOCK_IN_PLL64M = 0,
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APC_CLOCK_IN_PLLAPC,
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APC_CLOCK_IN_LSB,
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APC_CLOCK_IN_DISABLE,
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};
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#define UART_CLOCK_IN(x)
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//for MACRO - UART_CLOCK_IN
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enum {
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UART_CLOCK_IN_PLL48M = 0,
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UART_CLOCK_IN_OSC,
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UART_CLOCK_IN_LSB,
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UART_CLOCK_IN_DISABLE,
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};
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#define BT_CLOCK_IN(x)
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//for MACRO - BT_CLOCK_IN
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enum {
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BT_CLOCK_IN_PLL64M = 0,
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BT_CLOCK_IN_DISABLE,
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BT_CLOCK_IN_LSB,
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BT_CLOCK_IN_DISABLE_PAD,
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};
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#define MEM_CLOCK_STATUS(x)
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//for MACRO - MEM_CLOCK_STATUS
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enum {
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MEM_CLOCK_IDLE = 0,
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MEM_CLOCK_ALWAYS_ON,
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};
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#define OTP_CLOCK_ENABLE(x)
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//for MACRO - OTP_CLOCK_ENABLE
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enum {
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OTP_CLOCK_ENABLE = 0,
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OTP_CLOCK_DISABLE,
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};
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#define SFC_CLOCK_DELAY(x)
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#define PLL_SYS_SEL(x)
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//for MACRO - PLL_SYS_SEL
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enum {
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PLL_SYS_SEL_PLL192M = 0,
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PLL_SYS_SEL_PLL137M,
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PLL_SYS_SEL_PLL480M,
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PLL_SYS_SEL_DISABLE,
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};
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#define PLL_SYS_DIV(x)
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//for MACRO - PLL_SYS_DIV
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enum {
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PLL_SYS_DIV1 = 0,
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PLL_SYS_DIV3,
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PLL_SYS_DIV5,
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PLL_SYS_DIV7,
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PLL_SYS_DIV1X2 = 4,
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PLL_SYS_DIV3X2,
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PLL_SYS_DIV5X2,
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PLL_SYS_DIV7X2,
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PLL_SYS_DIV1X4 = 8,
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PLL_SYS_DIV3X4,
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PLL_SYS_DIV5X4,
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PLL_SYS_DIV7X4,
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PLL_SYS_DIV1X8 = 12,
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PLL_SYS_DIV3X8,
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PLL_SYS_DIV5X8,
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PLL_SYS_DIV7X8,
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};
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#define PLL_APC_SEL(x)
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//for MACRO - PLL_APC_SEL
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enum {
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PLL_APC_SEL_PLL192M = 0,
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PLL_APC_SEL_PLL137M,
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PLL_APC_SEL_DISABLE,
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};
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#define PLL_APC_DIV(x)
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//for MACRO - PLL_APC_DIV
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enum {
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PLL_APC_DIV1 = 0,
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PLL_APC_DIV3,
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PLL_APC_DIV5,
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PLL_APC_DIV7,
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PLL_APC_DIV1X2 = 4,
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PLL_APC_DIV3X2,
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PLL_APC_DIV5X2,
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PLL_APC_DIV7X2,
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PLL_APC_DIV1X4 = 8,
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PLL_APC_DIV3X4,
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PLL_APC_DIV5X4,
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PLL_APC_DIV7X4,
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PLL_APC_DIV1X8 = 12,
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PLL_APC_DIV3X8,
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PLL_APC_DIV5X8,
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PLL_APC_DIV7X8,
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};
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#define PLL_ALNK_SEL(x)
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//for MACRO - PLL_ALNK_SEL
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enum {
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PLL_ALNK_192M_DIV17 = 0,
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PLL_ALNK_480M_DIV39,
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};
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#define PLL_EN(x)
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#define PLL_REST(x)
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#define PLL_DIVn(x)
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#define PLL_DIVn_EN(x)
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#define PLL_REF_SEL(x)
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//for MACRO - PLL_RSEL
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enum {
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PLL_REF_SEL_BTOSC = 0, //bt
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PLL_REF_SEL_RTOSC, //rt
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PLL_REF_SEL_PAT = 3,
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};
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#define PLL_TEST(x)
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#define PLL_DSMS(x)
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#define PLL_DSM_TSEL(x)
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#define PLL_DSM_RSEL(x)
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#define PLL_DSM_MSEL(x)
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#define PLL_DIVSEL(x)
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//for MACRO - PLL_RSEL
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enum {
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PLL_DIVIDER_INTE = 0,
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PLL_DIVIDER_FRAC,
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};
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#define PLL_PFD(x)
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#define PLL_ICP(x)
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#define PLL_LPFR2(x)
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#define PLL_LPFR3(x)
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#define PLL_RSEL(x)
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//for MACRO - PLL_RSEL
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enum {
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PLL_RSEL_BTOSC_DIFF = 0,
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PLL_RSEL_RTOSC_DIFF,
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PLL_RSEL_PLL_REF_SEL,
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};
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#define PLL_DIVm(x)
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#define PLL_LD012A(x)
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#define PLL_LDO12D(x)
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#define PLL_IVCO(x)
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#define PLL_LDO_BYPASS(x)
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#define PLL_TSSEL(x)
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#define PLL_TSOE(x)
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#define PLL_CLK480M_OE(x)
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#define PLL_CLK320M_OE(x)
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#define PLL_CLK192M_OE(x)
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#define PLL_CLK137M_OE(x)
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#define PLL_CLK107M_OE(x)
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#define PLL_FRAC(x)
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#define PLL_DMAX(x)
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#define PLL_DMIN(x)
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#define PLL_DSTP(x)
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#define HSB_CLK_DIV(x)
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#define LSB_CLK_DIV(x)
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#define OTP_CLK_DIV(x)
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#else
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#define RC_EN(x) SFR(JL_CLOCK->CLK_CON0, 0, 1, x)
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#define RCH_EN(x) SFR(JL_CLOCK->CLK_CON0, 1, 1, x)
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//for MACRO - RCH_EN
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enum {
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RCH_EN_250K = 0,
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RCH_EN_16M,
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};
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#define TEST_SEL(x) SFR(JL_CLOCK->CLK_CON0, 2, 2, x)
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//for MACRO - TS_SEL
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enum {
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TS_SEL_IN_MAIN = 0,
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TS_SEL_IN_PAT,
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};
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#define OSC_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON0, 4, 2, x)
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//for MACRO - OSC_CLOCK_IN
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enum {
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OSC_CLOCK_IN_BT_OSC = 0,
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OSC_CLOCK_IN_RESERVED,
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OSC_CLOCK_IN_RTOSC_L,
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OSC_CLOCK_IN_PAT,
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};
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#define MAIN_CLOCK_SEL(x) SFR(JL_CLOCK->CLK_CON0, 6, 3, x)
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//for MACRO - CLOCK_IN
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enum {
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MAIN_CLOCK_IN_RC = 0,
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MAIN_CLOCK_IN_BTOSC = 4,
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MAIN_CLOCK_IN_RESERVED,
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MAIN_CLOCK_IN_RTOSC_L,
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MAIN_CLOCK_IN_PLL,
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};
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#define SFR_MODE(x) SFR(JL_CLOCK->CLK_CON0, 9, 1, x)
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enum {
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SFR_CLOCK_IDLE = 0,
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SFR_CLOCK_ALWAYS_ON,
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};
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#define PC0_CLOCK_OUT(x) SFR(JL_CLOCK->CLK_CON0, 10, 3, x)
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#define PA4_CLOCK_OUT(x) SFR(JL_CLOCK->CLK_CON0, 13, 3, x)
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#define USB_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 0, 2, x)
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//for MACRO - USB_CLOCK_IN
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enum {
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USB_CLOCK_IN_PLL48M = 0,
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USB_CLOCK_IN_OSC,
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USB_CLOCK_IN_LSB,
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USB_CLOCK_IN_DISABLE,
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};
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#define DAC_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 2, 2, x)
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//for MACRO - DAC_CLOCK_IN
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enum {
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DAC_CLOCK_IN_PLL24M = 0,
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DAC_CLOCK_IN_OSC,
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DAC_CLOCK_IN_LSB,
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DAC_CLOCK_IN_DISABLE,
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};
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#define GPCNT_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 4, 3, x)
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//for MACRO - DAC_CLOCK_IN
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enum {
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GPCNT_CLOCK_IN_NULL = 0,
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GPCNT_CLOCK_IN_SRC,
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GPCNT_CLOCK_IN_SFC,
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GPCNT_CLOCK_IN_HSB,
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GPCNT_CLOCK_IN_NULL0,
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GPCNT_CLOCK_IN_AUDIO,
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GPCNT_CLOCK_IN_WL,
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GPCNT_CLOCK_IN_USB,
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};
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#define UART_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 10, 2, x)
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//for MACRO - UART_CLOCK_IN
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enum {
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UART_CLOCK_IN_OSC = 0,
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UART_CLOCK_IN_PLL48M,
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UART_CLOCK_IN_LSB,
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UART_CLOCK_IN_DISABLE,
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};
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#define WL_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 14, 2, x)
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//for MACRO - BT_CLOCK_IN
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enum {
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WL_CLOCK_IN_PLL48M = 0,
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WL_CLOCK_IN_LSB = 2,
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WL_CLOCK_IN_DISABLE_PAD,
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};
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#define WL2_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 14, 2, x)
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//for MACRO - BT_CLOCK_IN
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enum {
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WL2_CLOCK_IN_PLL96M = 0,
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WL2_CLOCK_IN_PLL64M,
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WL2_CLOCK_IN_LSB,
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W2L_CLOCK_IN_DISABLE_PAD,
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};
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#define MEM_CLOCK_STATUS(x) SFR(JL_CLOCK->CLK_CON1, 16, 1, x)
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//for MACRO - MEM_CLOCK_STATUS
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enum {
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MEM_CLOCK_IDLE = 0,
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MEM_CLOCK_ALWAYS_ON,
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};
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#define SFC_CLOCK_DELAY(x) SFR(JL_CLOCK->CLK_CON1, 28, 2, x)
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#if 0 //
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#define PLL_SYS_SEL(x) SFR(JL_CLOCK->CLK_CON2, 0, 2, x)
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//for MACRO - PLL_SYS_SEL
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enum {
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PLL_SYS_SEL_PLL192M = 0,
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PLL_SYS_SEL_PLL137M,
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PLL_SYS_SEL_PLL320M,
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PLL_SYS_SEL_PLL480M,
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};
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#define PLL_SYS_DIV(x) SFR(JL_CLOCK->CLK_CON2, 4, 4, x)
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//for MACRO - PLL_SYS_DIV
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enum {
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PLL_SYS_DIV1 = 0,
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PLL_SYS_DIV3,
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PLL_SYS_DIV5,
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PLL_SYS_DIV7,
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PLL_SYS_DIV1X2 = 4,
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PLL_SYS_DIV3X2,
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PLL_SYS_DIV5X2,
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PLL_SYS_DIV7X2,
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PLL_SYS_DIV1X4 = 8,
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PLL_SYS_DIV3X4,
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PLL_SYS_DIV5X4,
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PLL_SYS_DIV7X4,
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PLL_SYS_DIV1X8 = 12,
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PLL_SYS_DIV3X8,
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PLL_SYS_DIV5X8,
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PLL_SYS_DIV7X8,
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};
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#define PLL_ALNK_EN(x) SFR(JL_CLOCK->CLK_CON2, 9, 1, x)
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#define PLL_ALNK_SEL(x) SFR(JL_CLOCK->CLK_CON2, 8, 1, x)
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//for MACRO - PLL_ALNK_SEL
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enum {
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PLL_ALNK_192M_DIV17 = 0,
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PLL_ALNK_160M_DIV13,
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};
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#define PLL_ALNK1_EN(x) SFR(JL_CLOCK->CLK_CON2, 11, 1, x)
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#define PLL_ALNK1_SEL(x) SFR(JL_CLOCK->CLK_CON2, 10, 1, x)
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//for MACRO - PLL_ALNK_SEL
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enum {
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PLL_ALNK1_192M_DIV17 = 0,
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PLL_ALNK1_160M_DIV13,
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};
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#define PLL_FM_SEL(x) SFR(JL_CLOCK->CLK_CON2, 12, 2, x)
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//for MACRO - PLL_APC_SEL
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enum {
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PLL_APC_SEL_PLL192M = 0,
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PLL_APC_SEL_PLL137M,
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PLL_APC_SEL_PLL107M,
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PLL_APC_SEL_DISABLE,
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};
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#define PLL_EN(x) SFR(JL_CLOCK->PLL_CON, 0, 1, x)
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#define PLL_REST(x) SFR(JL_CLOCK->PLL_CON, 1, 1, x)
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#define PLL_DIVn(x) SFR(JL_CLOCK->PLL_CON, 2, 5, x)
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#define PLL_REF_SEL(x) SFR(JL_CLOCK->PLL_CON, 7, 1, x)
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//for MACRO - PLL_REF_SEL
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enum {
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PLL_REF_SEL_BTOSC = 0, //btosc
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PLL_REF_SEL_RCLK,
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};
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#define PLL_DIVn_EN(x) SFR(JL_CLOCK->PLL_CON, 8, 2, x)
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//for MACRO - PLL_DIVn_EN
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enum {
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PLL_DIVn_EN_X2 = 0,
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PLL_DIVn_DIS_DIV1,
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PLL_DIVn_EN2_33,
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};
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#define PLL_TEST(x) SFR(JL_CLOCK->PLL_CON, 10, 1, x)
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#define PLL_PFD(x) SFR(JL_CLOCK->PLL_CON, 22, 2, x)
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#define PLL_ICP(x) SFR(JL_CLOCK->PLL_CON, 24, 2, x)
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#define PLL_LPFR2(x) SFR(JL_CLOCK->PLL_CON, 26, 2, x)
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#define PLL_RSEL(x) SFR(JL_CLOCK->PLL_CON, 30, 2, x)
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//for MACRO - PLL_RSEL
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enum {
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PLL_RSEL_RCH = 1, //
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PLL_RSEL_DPLL_CLK = 2,
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PLL_RSEL_PAT_CLK = 3,
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};
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#define PLL_FBDS(x) SFR(JL_CLOCK->PLL_CON1, 0, 12, x)
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#define PLL_IVCO(x) SFR(JL_CLOCK->PLL_CON1, 12, 3, x)
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#define PLL_LDO_BYPASS(x) SFR(JL_CLOCK->PLL_CON1, 15, 1, x)
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#define PLL_TSSEL(x) SFR(JL_CLOCK->PLL_CON1, 16, 2, x)
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#define PLL_TSOE(x) SFR(JL_CLOCK->PLL_CON1, 18, 1, x)
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#define PLL_EN200K(x) SFR(JL_CLOCK->PLL_CON1, 19, 1, x)
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#define PLL_LDO12A(x) SFR(JL_CLOCK->PLL_CON1, 20, 2, x)
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#define PLL_LDO12D(x) SFR(JL_CLOCK->PLL_CON1, 22, 2, x)
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#define PLL_CLK480M_OE(x) SFR(JL_CLOCK->PLL_CON1, 24, 1, x)
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#define PLL_CLK320M_OE(x) SFR(JL_CLOCK->PLL_CON1, 25, 1, x)
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#define PLL_CLK192M_OE(x) SFR(JL_CLOCK->PLL_CON1, 26, 1, x)
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#define PLL_CLK137M_OE(x) SFR(JL_CLOCK->PLL_CON1, 27, 1, x)
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#define PLL_CLK107M_OE(x) SFR(JL_CLOCK->PLL_CON1, 28, 1, x)
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#define HSB_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 0, 8, x)
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#define LSB_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 8, 3, x)
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#define SFC_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 12, 3, x)
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#endif
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/********************************************************************************/
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#endif
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#endif
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