1193 lines
39 KiB
C
1193 lines
39 KiB
C
#include "system/includes.h"
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#include "os/os_api.h"
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#include "database.h"
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#include "asm/crc16.h"
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#include "http/http_cli.h"
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#include "fs/fs.h"
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#include "app_config.h"
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#include "system/init.h"
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#include "device/device.h"
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extern void early_puts(char *s);
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void ram0_wr_test(void)
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{
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while (1) {
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for (int i = 0; i < 0x70000 / 4; i++) {
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*((volatile u32 *)(0x1c70000 - 4 * i)) = 0x12345678;
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if (*((volatile u32 *)(0x1c70000 - 4 * i)) != 0x12345678) {
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early_puts("N");
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}
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}
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}
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}
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static u8 dma_buf_cacheram[27 * 1024] ALIGNE(32) sec(.memp_memory_x);
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static void crc16_cacheram_test(void)
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{
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u16 ret;
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while (1) {
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for (int i = 0; i < sizeof(dma_buf_cacheram) - 2; i++) {
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dma_buf_cacheram[i] = (u8)JL_RAND->R64H;
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}
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ret = CRC16(dma_buf_cacheram, sizeof(dma_buf_cacheram) - 2);
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/* printf("ret1 = 0x%x\n", ret); */
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dma_buf_cacheram[sizeof(dma_buf_cacheram) - 2] = (ret >> 8 & 0x00ff);
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/* printf("ret2 = 0x%x\n", dma_buf_cacheram[sizeof(dma_buf_cacheram) - 2]); */
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dma_buf_cacheram[sizeof(dma_buf_cacheram) - 1] = (ret & 0x00ff);
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/* printf("ret3 = 0x%x\n", dma_buf_cacheram[sizeof(dma_buf_cacheram) - 1]); */
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ret = CRC16(dma_buf_cacheram, sizeof(dma_buf_cacheram));
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/* printf("ret = 0x%x\n", ret); */
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if (ret) {
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put_buf(dma_buf_cacheram, sizeof(dma_buf_cacheram));
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ASSERT(0);
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}
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}
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}
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___interrupt
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static void aes_isr(void)
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{
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if (JL_AES->CON & BIT(5)) {
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JL_AES->CON |= BIT(13);
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puts("111\n");
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}
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if (JL_AES->CON & BIT(2)) {
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JL_AES->CON |= BIT(12);
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puts("222\n");
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}
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if (JL_AES->CON & BIT(3)) {
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JL_AES->CON |= BIT(11);
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puts("333\n");
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}
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}
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___interrupt
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static void sha_isr(void)
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{
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if (JL_SHA->CON & BIT(15)) {
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JL_SHA->CON |= BIT(14);
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puts("000\n");
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}
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}
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void aes_sha_128_256_test(void)
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{
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#if 0
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JL_SHA->CON |= BIT(2);
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request_irq(IRQ_AES_IDX, 2, aes_isr, 0);
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JL_AES->CON |= (BIT(8) | BIT(9) | BIT(10));
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request_irq(IRQ_SHA_IDX, 2, sha_isr, 0);
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#endif
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int mbedtls_aes_self_test(int verbose);
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int mbedtls_sha1_self_test(int verbose);
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int mbedtls_sha256_self_test(int verbose);
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ASSERT(mbedtls_aes_self_test(0) == 0);
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ASSERT(mbedtls_sha1_self_test(0) == 0);
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ASSERT(mbedtls_sha256_self_test(0) == 0);
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}
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void vm_write_read_test(void)
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{
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static char vm_buf[252];
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u16 crc1 = 0;
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u16 crc2 = 0;
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while (1) {
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for (int i = 0; i < sizeof(vm_buf); ++i) {
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vm_buf[i] = JL_RAND->R64L;
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}
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crc1 = CRC16(vm_buf, sizeof(vm_buf));
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if (db_update_buffer(9, vm_buf, sizeof(vm_buf)) < 0) {
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puts("buffer write fail !\n");
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}
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memset(vm_buf, 0, sizeof(vm_buf));
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if (db_select_buffer(9, vm_buf, sizeof(vm_buf)) < 0) {
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puts("buffer read fail !\n");
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}
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crc2 = CRC16(vm_buf, sizeof(vm_buf));
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if (crc1 != crc2) {
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printf("crc1 : 0x%x != crc2 : 0x%x\n", crc1, crc2);
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}
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os_time_dly(10);
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}
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}
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static void fs_write_test()
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{
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#define FILE_SIZE 20 * 1024 * 1024
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static u8 write_buf[32 * 1024 + 500];
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for (int step = 0; step < 10; step++) {
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int wlen = 1;
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FILE *f = fopen(CONFIG_ROOT_PATH"wt_001.m", "w+");
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if (!f) {
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return;
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}
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memset(write_buf, (0x5A + step) & 0xff, sizeof(write_buf));
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for (int i = 0; i < FILE_SIZE;) {
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int len = fwrite(f, write_buf, wlen);
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if (len != wlen) {
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printf("fwrite: %x, %x, %x\n", i, len, wlen);
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fclose(f);
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while (1);
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return;
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}
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i += wlen;
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if (i == FILE_SIZE) {
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break;
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}
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wlen += jiffies % sizeof(write_buf);
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if (wlen > sizeof(write_buf)) {
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wlen = 2;
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}
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if (i + wlen > FILE_SIZE) {
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wlen = FILE_SIZE - i;
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}
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}
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printf("write_ok: %x, %x\n", wlen, fpos(f));
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fseek(f, 0, SEEK_SET);
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int rlen = 1024;
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for (int i = 0; i < FILE_SIZE; i += rlen) {
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memset(write_buf, 0, rlen);
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int len = fread(f, write_buf, rlen);
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if (len != rlen) {
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printf("fread: %x, %x, %x\n", len, rlen, fpos(f));
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fclose(f);
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while (1);
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return;
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}
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for (int i = 0; i < rlen; i++) {
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if (write_buf[i] != ((0x5A + step) & 0xff)) {
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printf("not eq: %x, %x, %x\n", write_buf[i], fpos(f), i);
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fclose(f);
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while (1);
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return;
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}
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}
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if (i + rlen >= FILE_SIZE) {
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rlen = FILE_SIZE - i;
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}
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}
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printf("---------------------fs_write_suss: %d\n", step);
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fdelete(f);
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}
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}
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static void fs_write_test2(void)
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{
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int ret1, ret2;
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static u8 buf[10240];
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for (int i = 0; i < 100; i++) {
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printf("\nfs_write_test num : %d addr : 0x%lx\n", i, i * sizeof(buf));
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for (int j = 0; j < sizeof(buf); j++) {
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buf[j] = (u8)j;
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}
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FILE *f = fopen(CONFIG_ROOT_PATH"test.txt", "w+");
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fseek(f, i * sizeof(buf), SEEK_SET);
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puts("---------fwrite\n");
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ret1 = fwrite(f, buf, sizeof(buf));
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#if 1
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fclose(f);
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f = fopen(CONFIG_ROOT_PATH"test.txt", "r");
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#endif
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fseek(f, i * sizeof(buf), SEEK_SET);
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memset(buf, 0, sizeof(buf));
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ret2 = fread(f, buf, sizeof(buf));
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for (int j = 0; j < sizeof(buf); j++) {
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if (buf[j] != (u8)j) {
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printf("fs_write_err: 0x%lx, 0x%x, 0x%x, ret1 : %d | ret2 : %d\n", i * sizeof(buf), j, buf[j], ret1, ret2);
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fclose(f);
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put_buf(buf, sizeof(buf));
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return;
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}
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}
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fclose(f);
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}
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}
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static void exfat_read_test(void)
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{
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u8 name[128];
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struct vfscan *fs;
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fs = fscan(CONFIG_ROOT_PATH, "-tTXT -sn");
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if (fs == NULL) {
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log_e("fscan_faild\n");
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return;
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}
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printf("fscan: file_number = %d\n", fs->file_number);;
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FILE *file = fselect(fs, FSEL_FIRST_FILE, 0);
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if (file) {
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fget_name(file, name, sizeof(name));
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printf("file_name: %s\n", name);
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}
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fclose(file);
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fscan_release(fs);
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}
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extern int storage_device_ready();
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static void fs_test_task(void *p)
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{
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OS_SEM sem;
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os_sem_create(&sem, 0);
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while (1) {
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if (!storage_device_ready()) {
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os_time_dly(10);
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continue;
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}
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fs_write_test();
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fs_write_test2();
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exfat_read_test();
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os_sem_pend(&sem, 0);
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}
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}
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static int fs_test_init()
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{
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task_create(fs_test_task, NULL, "fs_test");
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return 0;
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}
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/* late_initcall(fs_test_init); */
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#include "device/iic.h"
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static void *iic1_dev_handel;
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#define _24CXX_HARDADDR_DEAL(addr) (addr/MEM_SIZE+0)
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//芯片基本信息
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#define MEM_SIZE 0x0080
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//芯片常量
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#define DEV_24CXX_MAIN_ADDR 0xA0
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#define DEV_24CXX_READ 0x01
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#define DEV_24CXX_WRITE 0x00
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#define _24_ADDR 0
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static void _24cxx_writebyte(u32 addr, u8 data)
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{
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int err = 0;
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err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_TX_WITH_START_BIT, DEV_24CXX_MAIN_ADDR | (_24CXX_HARDADDR_DEAL(addr) << 1) | DEV_24CXX_WRITE);
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if (err) {
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printf("IIC_IOCTL_TX_WITH_START_BIT FIAL\n");
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return;
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}
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err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_TX, addr & (MEM_SIZE - 1));
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if (err) {
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printf("IIC_IOCTL_TX FIAL\n");
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return;
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}
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err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_TX_WITH_STOP_BIT, data);
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if (err) {
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printf("IIC_IOCTL_TX_WITH_STOP_BIT FIAL\n");
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return;
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}
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}
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static u8 _24cxx_readbyte(u32 addr)
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{
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int err = 0;
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unsigned char temp;
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err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_TX_WITH_START_BIT, DEV_24CXX_MAIN_ADDR | (_24CXX_HARDADDR_DEAL(addr) << 1) | DEV_24CXX_WRITE);
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if (err) {
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printf("IIC_IOCTL_TX_WITH_START_BIT FIAL\n");
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return -1;
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}
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err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_TX, addr & (MEM_SIZE - 1));
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/* err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_TX_WITH_STOP_BIT, addr & (MEM_SIZE - 1)); */
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if (err) {
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printf("IIC_IOCTL_TX FIAL\n");
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return -1;
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}
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err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_TX_WITH_START_BIT, DEV_24CXX_MAIN_ADDR | (_24CXX_HARDADDR_DEAL(addr) << 1) | DEV_24CXX_READ);
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if (err) {
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printf("IIC_IOCTL_TX_WITH_START_BIT FIAL\n");
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return -1;
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}
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err = dev_ioctl(iic1_dev_handel, IIC_IOCTL_RX_WITH_STOP_BIT, (int)&temp);
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if (err) {
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printf("IIC_IOCTL_RX_WITH_STOP_BIT FIAL\n");
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return -1;
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}
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return temp;
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}
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___interrupt
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static void iic_isr(void)
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{
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if (JL_IIC->CON0 & BIT(13)) {
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JL_IIC->CON0 |= BIT(12);
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puts("111\n");
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}
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if (JL_IIC->CON0 & BIT(15)) {
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JL_IIC->CON0 |= BIT(14);
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puts("222\n");
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}
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}
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static void iic_24cxx_test(void)
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{
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u8 test_buf[0x80];
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u8 res = 0;
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iic1_dev_handel = dev_open("iic1", NULL);
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if (!iic1_dev_handel) {
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printf("iic0 dev open err\n");
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ASSERT(0);
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}
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#if 0
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request_irq(IRQ_IIC_IDX, 2, iic_isr, 0);
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JL_IIC->CON0 |= BIT(8);
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#endif
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/* printf(" iic open ok!\n"); */
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#if 0
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for (u32 i = 0; i < sizeof(test_buf); i++) {
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/* test_buf[i] = 0x20 + i; */
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test_buf[i] = JL_RAND->R64L;
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_24cxx_writebyte(i + _24_ADDR, test_buf[i]);
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delay(48000);
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res = _24cxx_readbyte(i + _24_ADDR);
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if (res != test_buf[i]) {
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/* gpio_direction_output(IO_PORTH_02, 1); */
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printf("\n_24cxx_writebyte[%d] = 0x%x \n", i, test_buf[i]);
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printf("_24CXXX_ReadByte[%d] = 0x%x\n", i, res);
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printf("test fail!\n");
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/* gpio_direction_output(IO_PORTH_02, 0); */
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/* while (1); */
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}
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delay(48000);
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}
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#else
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static u8 i = 0;
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test_buf[i] = JL_RAND->R64L;
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dev_ioctl(iic1_dev_handel, IIC_IOCTL_START, 0);
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_24cxx_writebyte(i + _24_ADDR, test_buf[i]);
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dev_ioctl(iic1_dev_handel, IIC_IOCTL_STOP, 0);
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os_time_dly(1);
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dev_ioctl(iic1_dev_handel, IIC_IOCTL_START, 0);
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res = _24cxx_readbyte(i + _24_ADDR);
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dev_ioctl(iic1_dev_handel, IIC_IOCTL_STOP, 0);
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if (res != test_buf[i]) {
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/* gpio_direction_output(IO_PORTH_02, 1); */
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printf("\n_24cxx_writebyte[%d] = 0x%x \n", i, test_buf[i]);
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printf("_24CXXX_ReadByte[%d] = 0x%x\n", i, res);
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printf("test fail!\n");
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/* gpio_direction_output(IO_PORTH_02, 0); */
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while (1);
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}
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if (++i >= 128) {
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i = 0;
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}
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#endif
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dev_close(iic1_dev_handel);
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iic1_dev_handel = NULL;
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/* printf("iic test end!\n"); */
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}
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#if 0
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#include "../cpu/WL80/dvp_lcd_driver/lcd_st7735s.h"
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#define LCD_SHOW_INTERVAL_TIME 1000
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static void pap_lcd_test(void)
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{
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volatile u16 i = 0;
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u32 cnt = 0;
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u16 color[] = {WHITE, BLACK, BLUE, BRED, GRED, GBLUE, RED, MAGENTA, GREEN, CYAN, YELLOW, BROWN, BRRED, GRAY};
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ST7735S_init();
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while (1) {
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#if 1
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for (i = 0; i < sizeof(color) / sizeof(color[0]); i++) {
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printf("lcd test cnt : %d \n", ++cnt);
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ST7735S_clear_screen(color[i]);
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msleep(LCD_SHOW_INTERVAL_TIME);
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}
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#endif
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}
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}
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#endif
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/********************DMA COPY TEST*****************************/
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#if defined CONFIG_FPGA_TEST_ENABLE && !defined CONFIG_VIDEO_ENABLE
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#define DMA_COPY_TEST 1
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#else
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#define DMA_COPY_TEST 0
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#endif
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#if DMA_COPY_TEST && !defined CONFIG_NO_SDRAM_ENABLE
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#define DMA_TEST_BUF_SIZE (100 * 1024)
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static const u8 dma_tx_buf_rom[DMA_TEST_BUF_SIZE] ALIGNE(4) = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
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[1024 * 10] = 1, [1024 * 20] = 2, [1024 * 30] = 3, [1024 * 40] = 4, [1024 * 50] = 5,
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[1024 * 60] = 6, [1024 * 70] = 7, [1024 * 80] = 8, [1024 * 90] = 9, [1024 * 100 - 1] = 10,
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};
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static u8 dma_tx_buf_sdram[DMA_TEST_BUF_SIZE] ALIGNE(32);
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static u8 dma_rx_buf_sdram[DMA_TEST_BUF_SIZE] ALIGNE(32);
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static u8 dma_tx_buf_ram[DMA_TEST_BUF_SIZE] sec(.sram) ALIGNE(32);
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static u8 dma_rx_buf_ram[DMA_TEST_BUF_SIZE] sec(.sram) ALIGNE(32);
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static void dma_rom_to_sdram(void)
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{
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int ret = 0;
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|
|
dma_copy(dma_rx_buf_sdram, (void *)dma_tx_buf_rom, sizeof(dma_tx_buf_rom));
|
|
for (int i = 0; i < sizeof(dma_tx_buf_rom); ++i) {
|
|
if (dma_rx_buf_sdram[i] != dma_tx_buf_rom[i]) {
|
|
printf("dma_rom_to_sdram\n");
|
|
printf("dma_tx_buf_rom = 0x%x, dma_rx_buf_sdram = 0x%x\n", dma_tx_buf_rom[i], dma_rx_buf_sdram[i]);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void dma_rom_to_ram0(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
dma_copy(dma_rx_buf_ram, (void *)dma_tx_buf_rom, sizeof(dma_tx_buf_rom));
|
|
for (int i = 0; i < sizeof(dma_tx_buf_rom); ++i) {
|
|
if (dma_rx_buf_ram[i] != dma_tx_buf_rom[i]) {
|
|
printf("dma_rom_to_ram0\n");
|
|
printf("dma_tx_buf_rom = 0x%x, dma_rx_buf_ram = 0x%x\n", dma_tx_buf_rom[i], dma_rx_buf_ram[i]);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void dma_sdram_to_sdram(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_tx_buf_sdram) - 2; i++) {
|
|
dma_tx_buf_sdram[i] = (u8)JL_RAND->R64H;
|
|
}
|
|
ret = CRC16(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram) - 2);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_rx_buf_sdram, 0, sizeof(dma_rx_buf_sdram));
|
|
|
|
/* put_buf(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram)); */
|
|
/* printf("sizeof:%d\n", sizeof(dma_tx_buf_sdram)); */
|
|
/* puts("\n\n\n\n!!!\n\n\n"); */
|
|
dma_copy(dma_rx_buf_sdram, dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram));
|
|
/* put_buf(dma_rx_buf[j], sizeof(dma_rx_buf)); */
|
|
ret = CRC16(dma_rx_buf_sdram, sizeof(dma_tx_buf_sdram));
|
|
if (ret) {
|
|
printf("dma_sdram_to_sdram\n");
|
|
printf("dma_tx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)dma_tx_buf_sdram, ret);
|
|
printf("dma_rx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)dma_rx_buf_sdram, ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
static void dma_ram0_to_ram0(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_tx_buf_ram) - 2; i++) {
|
|
dma_tx_buf_ram[i] = (u8)JL_RAND->R64L;
|
|
}
|
|
ret = CRC16(dma_tx_buf_ram, sizeof(dma_tx_buf_ram) - 2);
|
|
dma_tx_buf_ram[sizeof(dma_tx_buf_ram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_tx_buf_ram[sizeof(dma_tx_buf_ram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_rx_buf_ram, 0, sizeof(dma_rx_buf_ram));
|
|
|
|
/* put_buf(dma_tx_buf_ram[j], sizeof(dma_tx_buf_ram[j])); */
|
|
/* printf("sizeof:%d\n", sizeof(dma_tx_buf_ram[0])); */
|
|
/* puts("\n\n\n\n!!!\n\n\n"); */
|
|
dma_copy(dma_rx_buf_ram, dma_tx_buf_ram, sizeof(dma_tx_buf_ram));
|
|
/* put_buf(dma_rx_buf_ram[j], sizeof(dma_rx_buf_ram[j])); */
|
|
ret = CRC16(dma_rx_buf_ram, sizeof(dma_tx_buf_ram));
|
|
if (ret) {
|
|
printf("dma_ram0_to_ram0 ret = 0x%x \n", ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
static void dma_ram0_to_sdram(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_tx_buf_ram) - 2; i++) {
|
|
dma_tx_buf_ram[i] = (u8)JL_RAND->R64L;
|
|
}
|
|
ret = CRC16(dma_tx_buf_ram, sizeof(dma_tx_buf_ram) - 2);
|
|
dma_tx_buf_ram[sizeof(dma_tx_buf_ram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_tx_buf_ram[sizeof(dma_tx_buf_ram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_rx_buf_sdram, 0, sizeof(dma_rx_buf_sdram));
|
|
/* put_buf(dma_tx_buf_ram[j], sizeof(dma_tx_buf_ram[j])); */
|
|
/* printf("sizeof:%d\n", sizeof(dma_tx_buf_ram[0])); */
|
|
/* puts("\n\n\n\n!!!\n\n\n"); */
|
|
dma_copy(dma_rx_buf_sdram, dma_tx_buf_ram, sizeof(dma_tx_buf_ram));
|
|
/* put_buf(dma_rx_buf_sdram[j], sizeof(dma_rx_buf_sdram[j])); */
|
|
ret = CRC16(dma_rx_buf_sdram, sizeof(dma_tx_buf_ram));
|
|
if (ret) {
|
|
printf("dma_ram0_to_sdram ret = 0x%x \n", ret);
|
|
}
|
|
}
|
|
|
|
static void dma_sdram_to_ram0(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_tx_buf_sdram) - 2; i++) {
|
|
dma_tx_buf_sdram[i] = (u8)JL_RAND->R64H;
|
|
}
|
|
ret = CRC16(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram) - 2);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_rx_buf_ram, 0, sizeof(dma_rx_buf_ram));
|
|
/* put_buf(dma_tx_buf_sdram[j], sizeof(dma_tx_buf_sdram[j])); */
|
|
/* printf("sizeof:%d\n", sizeof(dma_tx_buf_sdram[0])); */
|
|
/* puts("\n\n\n\n!!!\n\n\n"); */
|
|
dma_copy(dma_rx_buf_ram, dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram));
|
|
/* put_buf(dma_rx_buf_ram[j], sizeof(dma_rx_buf_ram[j])); */
|
|
ret = CRC16(dma_rx_buf_ram, sizeof(dma_tx_buf_sdram));
|
|
if (ret) {
|
|
printf("dma_sdram_to_ram0 ret = 0x%x \n", ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
static void dma_sdram_to_sdram_nocache(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_tx_buf_sdram) - 2; i++) {
|
|
dma_tx_buf_sdram[i] = (u8)JL_RAND->R64H;
|
|
}
|
|
ret = CRC16(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram) - 2);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_rx_buf_sdram, 0, sizeof(dma_rx_buf_sdram));
|
|
|
|
flush_dcache(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram));
|
|
flushinv_dcache(dma_rx_buf_sdram, sizeof(dma_rx_buf_sdram));
|
|
dma_copy((void *)NO_CACHE_ADDR(dma_rx_buf_sdram), (void *)NO_CACHE_ADDR(dma_tx_buf_sdram), sizeof(dma_tx_buf_sdram));
|
|
|
|
ret = CRC16(dma_rx_buf_sdram, sizeof(dma_rx_buf_sdram));
|
|
if (ret) {
|
|
printf("dma_sdram_to_sdram_nocache\n");
|
|
printf("dma_tx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)dma_tx_buf_sdram, ret);
|
|
printf("dma_rx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)dma_rx_buf_sdram, ret);
|
|
put_buf(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram));
|
|
put_buf(dma_rx_buf_sdram, sizeof(dma_rx_buf_sdram));
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
static void dma_ram0_to_sdram_nocache(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_tx_buf_ram) - 2; i++) {
|
|
dma_tx_buf_ram[i] = (u8)JL_RAND->R64L;
|
|
}
|
|
ret = CRC16(dma_tx_buf_ram, sizeof(dma_tx_buf_ram) - 2);
|
|
dma_tx_buf_ram[sizeof(dma_tx_buf_ram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_tx_buf_ram[sizeof(dma_tx_buf_ram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_rx_buf_sdram, 0, sizeof(dma_rx_buf_sdram));
|
|
|
|
flushinv_dcache(dma_rx_buf_sdram, sizeof(dma_rx_buf_sdram));
|
|
dma_copy((void *)NO_CACHE_ADDR(dma_rx_buf_sdram), dma_tx_buf_ram, sizeof(dma_tx_buf_ram));
|
|
|
|
ret = CRC16(dma_rx_buf_sdram, sizeof(dma_rx_buf_sdram));
|
|
if (ret) {
|
|
printf("dma_ram0_to_sdram_nocache ret = 0x%x \n", ret);
|
|
}
|
|
}
|
|
|
|
static void dma_sdram_to_ram0_nocache(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_tx_buf_sdram) - 2; i++) {
|
|
dma_tx_buf_sdram[i] = (u8)JL_RAND->R64H;
|
|
}
|
|
ret = CRC16(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram) - 2);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_tx_buf_sdram[sizeof(dma_tx_buf_sdram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_rx_buf_ram, 0, sizeof(dma_rx_buf_ram));
|
|
|
|
flush_dcache(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram));
|
|
dma_copy(dma_rx_buf_ram, (void *)NO_CACHE_ADDR(dma_tx_buf_sdram), sizeof(dma_tx_buf_sdram));
|
|
|
|
ret = CRC16(dma_rx_buf_ram, sizeof(dma_rx_buf_ram));
|
|
if (ret) {
|
|
printf("dma_sdram_to_ram0_nocache ret = 0x%x \n", ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
#if 1
|
|
|
|
static u8 large_dma_tx_buf_sdram[6 * 1024 * 1024] ALIGNE(32);
|
|
static u8 large_dma_rx_buf_sdram[6 * 1024 * 1024] ALIGNE(32);
|
|
|
|
static void large_dma_sdram_to_sdram(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(large_dma_tx_buf_sdram) - 2; i++) {
|
|
large_dma_tx_buf_sdram[i] = (u8)JL_RAND->R64L;
|
|
}
|
|
ret = CRC16(large_dma_tx_buf_sdram, sizeof(large_dma_tx_buf_sdram) - 2);
|
|
large_dma_tx_buf_sdram[sizeof(large_dma_tx_buf_sdram) - 2] = (ret >> 8 & 0x00ff);
|
|
large_dma_tx_buf_sdram[sizeof(large_dma_tx_buf_sdram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(large_dma_rx_buf_sdram, 0, sizeof(large_dma_rx_buf_sdram));
|
|
|
|
/* put_buf(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram)); */
|
|
/* printf("sizeof:%d\n", sizeof(dma_tx_buf_sdram)); */
|
|
/* puts("\n\n\n\n!!!\n\n\n"); */
|
|
dma_copy(large_dma_rx_buf_sdram, large_dma_tx_buf_sdram, sizeof(large_dma_tx_buf_sdram));
|
|
/* put_buf(dma_rx_buf[j], sizeof(dma_rx_buf)); */
|
|
ret = CRC16(large_dma_rx_buf_sdram, sizeof(large_dma_tx_buf_sdram));
|
|
if (ret) {
|
|
printf("large_dma_sdram_to_sdram\n");
|
|
printf("dma_tx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)large_dma_tx_buf_sdram, ret);
|
|
printf("dma_rx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)large_dma_rx_buf_sdram, ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
static void large_dma_sdram_to_sdram_nocache(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(large_dma_tx_buf_sdram) - 2; i++) {
|
|
large_dma_tx_buf_sdram[i] = (u8)JL_RAND->R64H;
|
|
}
|
|
ret = CRC16(large_dma_tx_buf_sdram, sizeof(large_dma_tx_buf_sdram) - 2);
|
|
large_dma_tx_buf_sdram[sizeof(large_dma_tx_buf_sdram) - 2] = (ret >> 8 & 0x00ff);
|
|
large_dma_tx_buf_sdram[sizeof(large_dma_tx_buf_sdram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(large_dma_rx_buf_sdram, 0, sizeof(large_dma_rx_buf_sdram));
|
|
|
|
flush_dcache(large_dma_tx_buf_sdram, sizeof(large_dma_tx_buf_sdram));
|
|
flushinv_dcache(large_dma_rx_buf_sdram, sizeof(large_dma_rx_buf_sdram));
|
|
dma_copy((void *)NO_CACHE_ADDR(large_dma_rx_buf_sdram), (void *)NO_CACHE_ADDR(large_dma_tx_buf_sdram), sizeof(large_dma_tx_buf_sdram));
|
|
|
|
ret = CRC16(large_dma_rx_buf_sdram, sizeof(large_dma_rx_buf_sdram));
|
|
if (ret) {
|
|
printf("large_dma_sdram_to_sdram_nocache\n");
|
|
printf("dma_tx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)large_dma_tx_buf_sdram, ret);
|
|
printf("dma_rx_buf_sdram = 0x%x, ret = 0x%x\n", (u32)large_dma_rx_buf_sdram, ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
#endif
|
|
|
|
#if 0
|
|
static u8 dma_buf_cacheram[27 * 1024] ALIGNE(32) sec(.memp_memory_x);
|
|
static u8 dma_buf_ram[27 * 1024] ALIGNE(32) sec(.sram);
|
|
|
|
static void dma_cacheram_to_ram(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_buf_cacheram) - 2; i++) {
|
|
dma_buf_cacheram[i] = (u8)JL_RAND->R64L;
|
|
}
|
|
ret = CRC16(dma_buf_cacheram, sizeof(dma_buf_cacheram) - 2);
|
|
dma_buf_cacheram[sizeof(dma_buf_cacheram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_buf_cacheram[sizeof(dma_buf_cacheram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_buf_ram, 0, sizeof(dma_buf_ram));
|
|
|
|
/* put_buf(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram)); */
|
|
/* printf("sizeof:%d\n", sizeof(dma_tx_buf_sdram)); */
|
|
/* puts("\n\n\n\n!!!\n\n\n"); */
|
|
dma_copy(dma_buf_ram, dma_buf_cacheram, sizeof(dma_buf_cacheram));
|
|
/* put_buf(dma_rx_buf[j], sizeof(dma_rx_buf)); */
|
|
ret = CRC16(dma_buf_ram, sizeof(dma_buf_cacheram));
|
|
if (ret) {
|
|
printf("dma_cacheram_to_ram\n");
|
|
printf("dma_buf_cacheram = 0x%x, ret = 0x%x\n", (u32)dma_buf_cacheram, ret);
|
|
printf("dma_buf_ram = 0x%x, ret = 0x%x\n", (u32)dma_buf_ram, ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
static void dma_ram_to_cacheram(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
for (int i = 0; i < sizeof(dma_buf_ram) - 2; i++) {
|
|
dma_buf_ram[i] = (u8)JL_RAND->R64H;
|
|
}
|
|
ret = CRC16(dma_buf_ram, sizeof(dma_buf_ram) - 2);
|
|
dma_buf_ram[sizeof(dma_buf_ram) - 2] = (ret >> 8 & 0x00ff);
|
|
dma_buf_ram[sizeof(dma_buf_ram) - 1] = (ret & 0x00ff);
|
|
|
|
memset(dma_buf_cacheram, 0, sizeof(dma_buf_cacheram));
|
|
|
|
/* put_buf(dma_tx_buf_sdram, sizeof(dma_tx_buf_sdram)); */
|
|
/* printf("sizeof:%d\n", sizeof(dma_tx_buf_sdram)); */
|
|
/* puts("\n\n\n\n!!!\n\n\n"); */
|
|
dma_copy(dma_buf_cacheram, dma_buf_ram, sizeof(dma_buf_ram));
|
|
/* put_buf(dma_rx_buf[j], sizeof(dma_rx_buf)); */
|
|
ret = CRC16(dma_buf_cacheram, sizeof(dma_buf_ram));
|
|
if (ret) {
|
|
printf("dma_cacheram_to_ram\n");
|
|
printf("dma_buf_ram = 0x%x, ret = 0x%x\n", (u32)dma_buf_ram, ret);
|
|
printf("dma_buf_cacheram = 0x%x, ret = 0x%x\n", (u32)dma_buf_cacheram, ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
/***********************************************************/
|
|
|
|
sec(.vm) volatile u32 debug_error_cnt = 0;
|
|
sec(.vm) volatile u32 debug_wait_flag = 0;
|
|
|
|
/********************DEBUG MSG TEST*****************************/
|
|
sec(.vm) static void debug_test_write(u32 addr, u32 len)
|
|
{
|
|
printf("test write addr 0x%x ---- 0x%x len : 0x%x \n", addr, addr + len, len);
|
|
if (addr == 0x4000000) {
|
|
corex2(0)->CACHE_CON &= ~(1 << 9); //disable sdram cache
|
|
}
|
|
for (u32 i = 0; i < len; ++i) {
|
|
*(volatile u8 *)(addr + i) = 0x5e;
|
|
while (!debug_wait_flag);
|
|
debug_wait_flag = 0;
|
|
}
|
|
if (addr == 0x4000000) {
|
|
corex2(0)->CACHE_CON |= (1 << 9); //enable sdram cache
|
|
}
|
|
printf("error cnt = 0x%x\n", debug_error_cnt);
|
|
debug_error_cnt = 0;
|
|
}
|
|
|
|
sec(.vm) static void debug_test_read(u32 addr, u32 len)
|
|
{
|
|
printf("test read addr 0x%x ---- 0x%x len : 0x%x \n", addr, addr + len, len);
|
|
if (addr == 0x4000000) {
|
|
corex2(0)->CACHE_CON &= ~(1 << 9); //disable rw cache
|
|
}
|
|
if (addr == 0x2000000) {
|
|
corex2(0)->CACHE_CON &= ~(1 << 8); //disable ro cache
|
|
}
|
|
for (u32 i = 0; i < len; ++i) {
|
|
volatile u8 data = *(volatile u8 *)(addr + i);
|
|
while (!debug_wait_flag);
|
|
debug_wait_flag = 0;
|
|
}
|
|
if (addr == 0x4000000) {
|
|
corex2(0)->CACHE_CON |= (1 << 9); //enable rw cache
|
|
}
|
|
if (addr == 0x2000000) {
|
|
corex2(0)->CACHE_CON |= (1 << 8); //enable ro cache
|
|
}
|
|
printf("error cnt = 0x%x\n", debug_error_cnt);
|
|
debug_error_cnt = 0;
|
|
}
|
|
|
|
sec(.vm) static void debug_test_write_limit(u32 addr, u32 len)
|
|
{
|
|
u8 volatile data;
|
|
printf("test write addr 0x%x ---- 0x%x len : 0x%x \n", addr, addr + len, len);
|
|
for (u32 i = 0; i < len; ++i) {
|
|
data = *(volatile u8 *)(addr + i);
|
|
*(volatile u8 *)(addr + i) = data;
|
|
while (!debug_wait_flag);
|
|
debug_wait_flag = 0;
|
|
}
|
|
printf("error cnt = 0x%x\n", debug_error_cnt);
|
|
debug_error_cnt = 0;
|
|
}
|
|
|
|
sec(.vm) static void debug_test_axi_wr_inv(u32 addr, u32 len)
|
|
{
|
|
printf("test write addr 0x%x ---- 0x%x len : 0x%x \n", addr, addr + len, len / 4);
|
|
JL_PLNK0->LEN = 2;
|
|
if (addr == 0x4000000) {
|
|
while (!(corex2(0)->CACHE_CON & BIT(14)));
|
|
corex2(0)->CACHE_CON &= ~(1 << 9); //disable sdram cache
|
|
while (!(corex2(0)->CACHE_CON & BIT(14)));
|
|
}
|
|
for (u32 i = 0; i < len; i += 4) {
|
|
JL_PLNK0->ADR = addr + i;
|
|
JL_PLNK0->CON = BIT(14) | BIT(0);
|
|
while (!debug_wait_flag);
|
|
debug_wait_flag = 0;
|
|
}
|
|
if (addr == 0x4000000) {
|
|
corex2(0)->CACHE_CON |= (1 << 9); //enable sdram cache
|
|
}
|
|
printf("error cnt = 0x%x\n", debug_error_cnt);
|
|
debug_error_cnt = 0;
|
|
}
|
|
|
|
sec(.vm) static void debug_test_axi_rd_inv(u32 addr, u32 len)
|
|
{
|
|
printf("test read addr 0x%x ---- 0x%x len : 0x%x \n", addr, addr + len, len / 4);
|
|
if (addr == 0x4000000) {
|
|
while (!(corex2(0)->CACHE_CON & BIT(14)));
|
|
corex2(0)->CACHE_CON &= ~(1 << 9); //disable rw cache
|
|
}
|
|
if (addr == 0x2000000) {
|
|
while (!(corex2(0)->CACHE_CON & BIT(14)));
|
|
corex2(0)->CACHE_CON &= ~(1 << 8); //disable ro cache
|
|
}
|
|
JL_ALNK0->LEN = 2;
|
|
JL_ALNK0->CON1 = BIT(0);
|
|
JL_ALNK0->CON3 = 0x23;
|
|
for (u32 i = 0; i < len; i += 4) {
|
|
JL_ALNK0->ADR0 = addr + i;
|
|
JL_ALNK0->CON0 = BIT(11);
|
|
while (!debug_wait_flag);
|
|
JL_ALNK0->CON2 = 0xf;
|
|
debug_wait_flag = 0;
|
|
}
|
|
if (addr == 0x4000000) {
|
|
corex2(0)->CACHE_CON |= (1 << 9); //enable rw cache
|
|
}
|
|
if (addr == 0x2000000) {
|
|
corex2(0)->CACHE_CON |= (1 << 8); //enable ro cache
|
|
}
|
|
printf("error cnt = 0x%x\n", debug_error_cnt);
|
|
debug_error_cnt = 0;
|
|
}
|
|
|
|
void debug_msg_test(void)
|
|
{
|
|
//测试CPU1需要将CPU0 HOLD住
|
|
#if 0
|
|
//c0_core_cache_winv and c1_core_cache_winv
|
|
debug_test_write(0x1c80000, 0x1d00000 - 0x1c80000);
|
|
debug_test_write(0x1d80000, 0x1e00000 - 0x1d80000);
|
|
debug_test_write(0x1e02800, 0x1edc000 - 0x1e02800);
|
|
debug_test_write(0x1f04000, 0x1f08000 - 0x1f04000);
|
|
debug_test_write(0x1f0a200, 0x1f0b000 - 0x1f0a200);
|
|
debug_test_write(0x1f0b200, 0x1f20000 - 0x1f0b200);
|
|
debug_test_write(0x1f20000, 0x1f28000 - 0x1f20000);
|
|
debug_test_write(0x1f28000, 0x1f30000 - 0x1f28000);
|
|
debug_test_write(0x1f30000, 0x2000000 - 0x1f30000);
|
|
debug_test_write(0x2000000, 0x4000000 - 0x2000000);
|
|
debug_test_write(0x4000000, 0x8000000 - 0x4000000);
|
|
|
|
//c0_core_cache_rinv and c1_core_cache_rinv
|
|
debug_test_read(0x1c80000, 0x1d00000 - 0x1c80000);
|
|
debug_test_read(0x1d80000, 0x1e00000 - 0x1d80000);
|
|
debug_test_read(0x1e02800, 0x1edc000 - 0x1e02800);
|
|
debug_test_read(0x1f04000, 0x1f08000 - 0x1f04000);
|
|
debug_test_read(0x1f0a200, 0x1f0b000 - 0x1f0a200);
|
|
debug_test_read(0x1f0b200, 0x1f20000 - 0x1f0b200);
|
|
debug_test_read(0x1f20000, 0x1f28000 - 0x1f20000);
|
|
debug_test_read(0x1f28000, 0x1f30000 - 0x1f28000);
|
|
debug_test_read(0x1f30000, 0x2000000 - 0x1f30000);
|
|
debug_test_read(0x2000000, 0x4000000 - 0x2000000);
|
|
debug_test_read(0x4000000, 0x8000000 - 0x4000000);
|
|
|
|
//cpu axi_wr_inv
|
|
debug_test_write(0, 0x10000 - 0);
|
|
debug_test_write(0x60000, 0x400000 - 0x60000);
|
|
debug_test_write(0x400000, 0x1bf0000 - 0x400000);
|
|
|
|
//cpu axi_rd_inv
|
|
debug_test_read(0, 0x10000 - 0);
|
|
debug_test_read(0x60000, 0x400000 - 0x60000);
|
|
debug_test_read(0x400000, 0x1bf0000 - 0x400000);
|
|
#endif
|
|
|
|
#if 0
|
|
//测试时debug_index需要放在sec(.vm)
|
|
cpu_write_range_limit((void *)0x1c00310, 0x1c7fe00 - 0x1c00310);
|
|
cpu_write_range_limit((void *)0x4000000, 0x4800000 - 0x4000000);
|
|
cpu_write_range_limit((void *)0x4800000, 0x5000000 - 0x4800000);
|
|
cpu_write_range_limit((void *)0x5000000, 0x5800000 - 0x5000000);
|
|
cpu_write_range_limit((void *)0x5800000, 0x6000000 - 0x5800000);
|
|
cpu_write_range_limit((void *)0x6000000, 0x6800000 - 0x6000000);
|
|
cpu_write_range_limit((void *)0x6800000, 0x7000000 - 0x6800000);
|
|
cpu_write_range_limit((void *)0x7000000, 0x8000000 - 0x7000000);
|
|
|
|
debug_test_write_limit(0x1c00310, 0x1c7fe00 - 0x1c00310);
|
|
debug_test_write_limit(0x4000000, 0x4800000 - 0x4000000);
|
|
debug_test_write_limit(0x4800000, 0x5000000 - 0x4800000);
|
|
debug_test_write_limit(0x5000000, 0x5800000 - 0x5000000);
|
|
debug_test_write_limit(0x5800000, 0x6000000 - 0x5800000);
|
|
debug_test_write_limit(0x6000000, 0x6800000 - 0x6000000);
|
|
debug_test_write_limit(0x6800000, 0x7000000 - 0x6800000);
|
|
debug_test_write_limit(0x7000000, 0x8000000 - 0x7000000);
|
|
#endif
|
|
|
|
#if 0
|
|
debug_test_axi_wr_inv(0, 0x10000 - 0);
|
|
debug_test_axi_wr_inv(0x60000, 0x400000 - 0x60000);
|
|
debug_test_axi_wr_inv(0x400000, 0x1bf0000 - 0x400000);
|
|
debug_test_axi_wr_inv(0x1c80000, 0x1d00000 - 0x1c80000);
|
|
debug_test_axi_wr_inv(0x1d80000, 0x1e00000 - 0x1d80000);
|
|
debug_test_axi_wr_inv(0x1e02800, 0x1edc000 - 0x1e02800);
|
|
debug_test_axi_wr_inv(0x1f04000, 0x1f08000 - 0x1f04000);
|
|
debug_test_axi_wr_inv(0x1f0a200, 0x1f0b000 - 0x1f0a200);
|
|
debug_test_axi_wr_inv(0x1f0b200, 0x1f20000 - 0x1f0b200);
|
|
debug_test_axi_wr_inv(0x1f20000, 0x1f28000 - 0x1f20000);
|
|
debug_test_axi_wr_inv(0x1f28000, 0x1f30000 - 0x1f28000);
|
|
debug_test_axi_wr_inv(0x1f30000, 0x2000000 - 0x1f30000);
|
|
debug_test_axi_wr_inv(0x2000000, 0x4000000 - 0x2000000);
|
|
debug_test_axi_wr_inv(0x4000000, 0x8000000 - 0x4000000);
|
|
#endif
|
|
|
|
#if 0
|
|
debug_test_axi_rd_inv(0, 0x10000 - 0);
|
|
debug_test_axi_rd_inv(0x60000, 0x400000 - 0x60000);
|
|
debug_test_axi_rd_inv(0x400000, 0x1bf0000 - 0x400000);
|
|
debug_test_axi_rd_inv(0x1c80000, 0x1d00000 - 0x1c80000);
|
|
debug_test_axi_rd_inv(0x1d80000, 0x1e00000 - 0x1d80000);
|
|
debug_test_axi_rd_inv(0x1e02800, 0x1edc000 - 0x1e02800);
|
|
debug_test_axi_rd_inv(0x1f04000, 0x1f08000 - 0x1f04000);
|
|
debug_test_axi_rd_inv(0x1f0a200, 0x1f0b000 - 0x1f0a200);
|
|
debug_test_axi_rd_inv(0x1f0b200, 0x1f20000 - 0x1f0b200);
|
|
debug_test_axi_rd_inv(0x1f20000, 0x1f28000 - 0x1f20000);
|
|
debug_test_axi_rd_inv(0x1f28000, 0x1f30000 - 0x1f28000);
|
|
debug_test_axi_rd_inv(0x1f30000, 0x1fffff8 - 0x1f30000);
|
|
debug_test_axi_rd_inv(0x2000000, 0x4000000 - 0x2000000);
|
|
debug_test_axi_rd_inv(0x4000000, 0x8000000 - 0x4000000);
|
|
#endif
|
|
|
|
#if 0
|
|
dev_write_range_limit(0, (void *)0x1c04b10, (void *)0x1c7fe00, 1, -1);
|
|
dev_write_range_limit(1, (void *)0x4000000, (void *)0x4800000, 1, -1);
|
|
dev_write_range_limit(2, (void *)0x4800000, (void *)0x5000000, 1, -1);
|
|
dev_write_range_limit(3, (void *)0x5000000, (void *)0x5800000, 1, -1);
|
|
dev_write_range_limit(4, (void *)0x5800000, (void *)0x6000000, 1, -1);
|
|
dev_write_range_limit(5, (void *)0x6000000, (void *)0x6800000, 1, -1);
|
|
dev_write_range_limit(6, (void *)0x6800000, (void *)0x7000000, 1, -1);
|
|
dev_write_range_limit(7, (void *)0x7000000, (void *)0x8000000, 1, -1);
|
|
|
|
//要小心外设改动stack和vm段
|
|
debug_test_axi_wr_inv(0x1c04b10, 0x1c7fcf0 - 0x1c04b10);
|
|
debug_test_axi_wr_inv(0x4000000, 0x4800000 - 0x4000000);
|
|
#if 0
|
|
debug_test_axi_wr_inv(0x4800000, 0x5000000 - 0x4800000);
|
|
debug_test_axi_wr_inv(0x5000000, 0x5800000 - 0x5000000);
|
|
debug_test_axi_wr_inv(0x5800000, 0x6000000 - 0x5800000);
|
|
debug_test_axi_wr_inv(0x6000000, 0x6800000 - 0x6000000);
|
|
debug_test_axi_wr_inv(0x6800000, 0x7000000 - 0x6800000);
|
|
debug_test_axi_wr_inv(0x7000000, 0x8000000 - 0x7000000);
|
|
#endif
|
|
#endif
|
|
|
|
#if 0
|
|
dev_write_range_limit(0, (void *)0x1c04b10, (void *)0x1c7fe00, 1, 0x53);
|
|
dev_write_range_limit(1, (void *)0x4000000, (void *)0x4800000, 1, 0x53);
|
|
dev_write_range_limit(2, (void *)0x4800000, (void *)0x5000000, 1, 0x53);
|
|
dev_write_range_limit(3, (void *)0x5000000, (void *)0x5800000, 1, 0x53);
|
|
dev_write_range_limit(4, (void *)0x5800000, (void *)0x6000000, 1, 0x53);
|
|
dev_write_range_limit(5, (void *)0x6000000, (void *)0x6800000, 1, 0x53);
|
|
dev_write_range_limit(6, (void *)0x6800000, (void *)0x7000000, 1, 0x53);
|
|
dev_write_range_limit(7, (void *)0x7000000, (void *)0x8000000, 1, 0x53);
|
|
|
|
//要小心外设改动stack和vm段
|
|
debug_test_axi_wr_inv(0x1c04b10, 0x1c7fcf0 - 0x1c04b10);
|
|
debug_test_axi_wr_inv(0x4000000, 0x4800000 - 0x4000000);
|
|
#if 0
|
|
debug_test_axi_wr_inv(0x4800000, 0x5000000 - 0x4800000);
|
|
debug_test_axi_wr_inv(0x5000000, 0x5800000 - 0x5000000);
|
|
debug_test_axi_wr_inv(0x5800000, 0x6000000 - 0x5800000);
|
|
debug_test_axi_wr_inv(0x6000000, 0x6800000 - 0x6000000);
|
|
debug_test_axi_wr_inv(0x6800000, 0x7000000 - 0x6800000);
|
|
debug_test_axi_wr_inv(0x7000000, 0x8000000 - 0x7000000);
|
|
#endif
|
|
#endif
|
|
|
|
#if 0
|
|
dev_write_range_limit(0, (void *)0x1c04b10, (void *)0x1c7fe00, 1, 0x51);
|
|
dev_write_range_limit(1, (void *)0x4000000, (void *)0x4800000, 1, 0x51);
|
|
dev_write_range_limit(2, (void *)0x4800000, (void *)0x5000000, 1, 0x51);
|
|
dev_write_range_limit(3, (void *)0x5000000, (void *)0x5800000, 1, 0x51);
|
|
dev_write_range_limit(4, (void *)0x5800000, (void *)0x6000000, 1, 0x51);
|
|
dev_write_range_limit(5, (void *)0x6000000, (void *)0x6800000, 1, 0x51);
|
|
dev_write_range_limit(6, (void *)0x6800000, (void *)0x7000000, 1, 0x51);
|
|
dev_write_range_limit(7, (void *)0x7000000, (void *)0x8000000, 1, 0x51);
|
|
|
|
//要小心外设改动stack和vm段
|
|
debug_test_axi_wr_inv(0x1c04b10, 0x1c7fcf0 - 0x1c04b10);
|
|
debug_test_axi_wr_inv(0x4000000, 0x4800000 - 0x4000000);
|
|
#if 0
|
|
debug_test_axi_wr_inv(0x4800000, 0x5000000 - 0x4800000);
|
|
debug_test_axi_wr_inv(0x5000000, 0x5800000 - 0x5000000);
|
|
debug_test_axi_wr_inv(0x5800000, 0x6000000 - 0x5800000);
|
|
debug_test_axi_wr_inv(0x6000000, 0x6800000 - 0x6000000);
|
|
debug_test_axi_wr_inv(0x6800000, 0x7000000 - 0x6800000);
|
|
debug_test_axi_wr_inv(0x7000000, 0x8000000 - 0x7000000);
|
|
#endif
|
|
#endif
|
|
|
|
#if 0
|
|
dev_write_range_limit(0, (void *)0x1c04b10, (void *)0x1c7fe00, 0, 0x51);
|
|
dev_write_range_limit(1, (void *)0x4000000, (void *)0x4800000, 0, 0x51);
|
|
dev_write_range_limit(2, (void *)0x4800000, (void *)0x5000000, 0, 0x51);
|
|
dev_write_range_limit(3, (void *)0x5000000, (void *)0x5800000, 0, 0x51);
|
|
dev_write_range_limit(4, (void *)0x5800000, (void *)0x6000000, 0, 0x51);
|
|
dev_write_range_limit(5, (void *)0x6000000, (void *)0x6800000, 0, 0x51);
|
|
dev_write_range_limit(6, (void *)0x6800000, (void *)0x7000000, 0, 0x51);
|
|
dev_write_range_limit(7, (void *)0x7000000, (void *)0x8000000, 0, 0x51);
|
|
|
|
//要小心外设改动stack和vm段
|
|
debug_test_axi_wr_inv(0x1c04b10, 0x1c7fcf0 - 0x1c04b10);
|
|
debug_test_axi_wr_inv(0x4000000, 0x4800000 - 0x4000000);
|
|
#if 0
|
|
debug_test_axi_wr_inv(0x4800000, 0x5000000 - 0x4800000);
|
|
debug_test_axi_wr_inv(0x5000000, 0x5800000 - 0x5000000);
|
|
debug_test_axi_wr_inv(0x5800000, 0x6000000 - 0x5800000);
|
|
debug_test_axi_wr_inv(0x6000000, 0x6800000 - 0x6000000);
|
|
debug_test_axi_wr_inv(0x6800000, 0x7000000 - 0x6800000);
|
|
debug_test_axi_wr_inv(0x7000000, 0x8000000 - 0x7000000);
|
|
#endif
|
|
#endif
|
|
}
|
|
/***************************************************************/
|
|
|
|
|
|
|
|
|
|
static const int uart_table[] = {
|
|
1200, 2400, 4800, 9600, 14400, 19200, 38400, 43000, 57600, 76800, 115200, 128000, 230400, 256000, 460800, 921600, 1382400
|
|
};
|
|
|
|
static struct uart_platform_data uart_data = {
|
|
.baudrate = 921600,
|
|
.tx_pin = IO_PORTA_03,
|
|
.rx_pin = IO_PORTA_04,
|
|
.flags = UART_DEBUG,
|
|
.irq = IRQ_UART0_IDX,
|
|
};
|
|
|
|
extern int uart_init(const struct uart_platform_data *data);
|
|
static void uart_baudrate_test(void)
|
|
{
|
|
static u8 num = 0;
|
|
u8 cnt = 0;
|
|
|
|
uart_init((const struct uart_platform_data *)&uart_data);
|
|
|
|
while (1) {
|
|
if (cnt == 30) {
|
|
cnt = 0;
|
|
printf("The next baudrate is %d, remember change the baudrate of computer!!!\n", uart_table[num]);
|
|
uart_data.baudrate = uart_table[num];
|
|
uart_init((const struct uart_platform_data *)&uart_data);
|
|
if (++num >= ARRAY_SIZE(uart_table)) {
|
|
num = 0;
|
|
}
|
|
os_time_dly(500);
|
|
}
|
|
cnt++;
|
|
printf("cnt:%d, cnt_addr:0x%x\n", cnt, (u32)&cnt);
|
|
}
|
|
}
|
|
|
|
static void wl80_test_task(void *p)
|
|
{
|
|
u32 cnt = 0;
|
|
|
|
os_time_dly(300);
|
|
|
|
while (1) {
|
|
printf("cnt:%d\n", cnt++);
|
|
|
|
os_time_dly(1);
|
|
|
|
iic_24cxx_test();
|
|
#ifdef CONFIG_NET_ENABLE
|
|
aes_sha_128_256_test();
|
|
#endif
|
|
if (cnt % 30 == 0) {
|
|
extern void pwm_led_test(void);
|
|
pwm_led_test();
|
|
}
|
|
#if DMA_COPY_TEST && !defined CONFIG_NO_SDRAM_ENABLE
|
|
dma_rom_to_sdram();
|
|
dma_rom_to_ram0();
|
|
dma_sdram_to_sdram();
|
|
dma_ram0_to_ram0();
|
|
dma_ram0_to_sdram();
|
|
dma_sdram_to_ram0();
|
|
dma_sdram_to_ram0_nocache();
|
|
dma_sdram_to_sdram_nocache();
|
|
dma_ram0_to_sdram_nocache();
|
|
large_dma_sdram_to_sdram_nocache();
|
|
large_dma_sdram_to_sdram();
|
|
#else
|
|
os_time_dly(100);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static int wl80_test_init()
|
|
{
|
|
return thread_fork("wl80_test", 0, 2048, 0, 0, wl80_test_task, NULL);
|
|
}
|
|
#ifdef CONFIG_FPGA_TEST_ENABLE
|
|
late_initcall(wl80_test_init);
|
|
#endif
|
|
|